Integrated circuit devices are being fabricated with semiconductor processes that operate at voltages of approximately 1.8 volts. However these integrated circuit devices may be part of electronic systems that operate with electronic accessory devices that require a higher voltage power source to function. In portable or mobile battery powered electronic devices a low dropout voltage regulator reduces the higher voltage of the battery to a safe operating voltage for the device requiring the lower voltage.
As is known in the art, a voltage regulator is a constant voltage source that adjusts its internal resistance to any occurring changes of load resistance to provide a constant voltage at the regulator output. FIG. 1 is a schematic diagram of a low dropout voltage regulator. The load resistance of the voltage regulator as shown is formed by the parallel combination of the equivalent series resistance RESR of the load capacitor CL and the load resistor RL.
In order to regulate the output voltage resulting from any changes is the load resistor RL, the internal resistance of the voltage regulator must be adjusted to maintain the output voltage 55 at the desired level. To accomplish this, the output voltage is sensed by the voltage divider formed by the series resistors R1 and R2. As is known, the feedback voltage VFB is the product of the output voltage 55 and the ratio of the resistor R2 and the sum of the series resistors R1 and R2. An error amplifier receives the feedback voltage VFB and compares it with a reference voltage VREF to generate an error voltage. The error voltage is amplified and conditioned by a pass gate driver circuit to create the output voltage of the error amplifier AERR.
The error amplifier AERR has a differential amplifier formed of the differential pair of PMOS transistors P1 and P2. The NMOS transistors N1 and N2 for the load devices for the differential pair of PMOS transistors P1 and P2. A biasing current source I1 provides the biasing current for the differential pair of transistors P1 and P2. The drains of the PMOS transistor P2 and the NMOS transistor N2 are connected to form the output terminal 13 of the differential pair of PMOS transistors P1 and P2 of the error amplifier AERR. The feedback voltage VFB that is developed at the common connection of the series resistors R1 and R2 is applied to the gate of the PMOS transistor P1. A reference voltage VREF is applied to the gate of the PMOS transistor P2. The difference in the feedback voltage VFB and the reference voltage VREF is developed at the output terminal 13 of the differential pair of transistors P4 and P5 of the error amplifier AERR as the error voltage VERR. The drain of the PMOS transistor P1 is connected to the drain and gate of the NMOS transistor N1 and the gate of the NMOS transistor N2. The sources of the NMOS transistors N1 and N2 are connected to the ground reference voltage source.
The error amplifier AERR provides an indication of the error between the feedback voltage VFB and the reference voltage VREF that is applied to gate of the PMOS pass transistor PPASS. The drain-to-source voltage (Vds) and the drain-to-source current (Ids) determine the equivalent internal resistance of the low dropout voltage regulator. As is known, the drain-to-source voltage (Vds) and the drain-to-source current (Ids) are determined by the transconductance of the PMOS pass transistor PPASS and the gate-to-source voltage (Vgs) of the PMOS pass transistor PPASS.
The dropout voltage of the low dropout regulator is normally defined the point at which the drain-to-source voltage (Vds) of the PMOS pass transistor PPASS is not changed when the gate-to-source voltage (Vgs) changes and the PMOS pass transistor PPASS is in saturation.
The size of the PMOS pass transistor PPASS is normally very large to provide the necessary current to the load resistance RL. Further the load capacitance CL and the miller capacitance of the PMOS pass transistor PPASS create a zero the right hand plane that may cause instability in the error amplifier AERR and cause oscillation in the output voltage. To alleviate the instabilities, the compensation capacitor CCOMP is placed between the gate and the drain of the PMOS pass transistor PPASS to shift the zero sufficiently high in frequency to not cause the instabilities.
In some instances, an accessory device may require a higher voltage or current to operate than is available to the device requiring the lower voltage. When this occurs, a control system for the electronic device will enable a bypass circuit for the low dropout regulator thus connecting the higher voltage power supply or battery to the accessory device.
FIG. 2 is a schematic diagram of a low dropout voltage regulator including a bypass circuit of the prior art. The low dropout voltage regulator has two separate loops to control operation in a low dropout voltage regulation mode and a bypass mode. When the bypass mode control loop is deactivated, the low dropout regulation mode is in operation providing the required regulated low voltage. When the bypass mode control loop is activated, the low dropout regulation mode is not in operation and the bypass mode control loop is driving the PMOS pass transistor such that the output voltage is approaching the voltage level of the battery power source. An analog multiplexer is used to select the signal to drive the gate of pass device depending on mode of operation.
The LDO control circuit 10, as described above, has an error amplifier 12 that receives the feedback voltage VFB and compares it with a reference voltage VREF to generate an error voltage VERR. The feedback voltage VFB is applied to a gate of a first PMOS transistor P1 of a differential pair of transistors P1 and P2 and the reference voltage VREF is applied to the gate of a second PMOS transistor P2 of a differential pair of PMOS transistors P1 and P2. The NMOS transistors N1 and N2 are configured as a current source load for the differential pair of PMOS transistors P1 and P2. The current source I1 provides the constant current for determining the error voltage VERR.
The error voltage VERR is applied to the pass gate driver circuit 14 to be amplified and conditioned to generate the gate control voltage 15. The pass gate driver circuit 14 has an NMOS transistor N3 that acts as the amplifier for the error voltage VERR. The current source I2 and the PMOS transistor P3 acts as the load circuit for the NMOS transistor N3 to generate the correct voltage level for the gate control voltage 15.
The gate control voltage 15 is an input to the analog multiplexer 20. The analog multiplexer 20 has two switches S1 and S2 that are alternately actuated and de-actuated for activating or bypassing the low dropout voltage operation. The gate control voltage 15 is applied to a first terminal of the switch S2. The second terminal of the switch S2 is connected to the gate 25 of the PMOS pass transistor PPASS. The source of the PMOS pass transistor PPASS is connected to a terminal of the battery power source VBAT and the drain of the PMOS pass transistor PPASS is connected to the output terminal 55 of the low dropout voltage regulator to provide the output voltage VOUT and output current 60 to the load 65 of the external electronic circuits connected to the output terminal of the low dropout voltage regulator. The output terminal of the low dropout voltage regulator is further connected to the voltage divider formed by the two series connected resistors R1 and R2. A first terminal of the resistor R1 is connected to the drain of the PMOS pass transistor PPASS. A second terminal of the resistor R1 is commonly connected to a first terminal of the resistor R2 to provide the feedback voltage VFB as described above. The second terminal of the resistor R2 is connected to the ground reference voltage source.
The enable signal 30 and the bypass signal 35 are applied from an external system controller (not shown) to the bypass control circuit 40. The bypass control circuit 40 generates a bypass gate control signal 50 that is transferred to a first terminal of the switch S1 of the analog multiplexer 20. The bypass signal 35 is connected to the control terminal of the switch S1 and the input of the inverter 22 of the analog multiplexer 20. The output of the inverter 22 is connected to the control terminal of the switch S2 to receive the inverse of the bypass control signal 35. When the enable signal 30 is activated and the bypass signal 30 is deactivated, the switch S1 is opened and the switch S2 is closed such that the gate control voltage 15 is transferred to the gate terminal 25 of the PMOS pass transistor PPASS. When the enable signal 30 and the bypass signal 30 are activated, the switch S1 is closed and the switch S2 is opened such that the bypass gate control signal 50 is transferred to the gate terminal 25 of the PMOS pass transistor PPASS. The LDO enable signal 45 is deactivated and the LDO control circuit 10 is disabled. When the LDO control circuit 10 is disabled the gate control voltage 15 is pulled to approximately the voltage level of the power supply voltage source VDD. The low dropout voltage regulator is operating in its bypass mode.
When the enable signal 30 is deactivated, the LDO control circuit 10 and the bypass control circuit 40 are both disabled. The low dropout voltage regulator is not operating.
FIG. 3 is a set of plots of signals at points within the low dropout voltage regulator including a bypass circuit of the prior art. At the time t1 the enable signal 30 is activated and the bypass control circuit 40 generates the LDO enable signal 45. The bypass signal 35 is deactivated. The LDO gate control signal 15 is transferred through the analog multiplexer 20 as the gate signal 25 to the gate of the PMOS pass transistor PPASS such that the PMOS pass transistor PPASS begins to conduct. At the time t2, the load current 60 is set to the current level as demanded by the load 65, when the output voltage level VOUT at the output terminal 55 has risen to the voltage level regulated by the low dropout voltage regulator.
At the time t3, the load in the form of another accessory requests additional power from the battery power source VBAT. A system controller (not shown) activates the bypass signal 35 and the bypass controller 25 deactivates the LDO enable signal 45. The LDO gate control signal 15 is deactivated and the gate signal is brought to the voltage level of the power supply voltage source VDD. The output voltage level 55 begins to decrease as the current required by the load 65 is drawn from the decoupling capacitors (not shown) attached with the load 65 to the output terminal of the low dropout voltage regulator. In the time between t3 and t4, the bypass control circuitry is biased with its internal nodes settling to desired potentials.
At the time t4, the bypass controller 20 activates the bypass gate control signal 50 and thus sets the gate signal 25 to turn on the PMOS pass transistor PPASS to a saturated condition. The output voltage VOUT at the output terminal 55 rises to a voltage level approaching the voltage level of the battery power source VBAT at the time t5.
In low dropout regulation mode, the analog multiplexer 20 selects the output of the low dropout regulator control circuit 10 to drive the PMOS pass transistor PPASS to provide the regulated low voltage to the output terminal 55. In bypass mode, the multiplexer 20 selects the output of bypass control circuit 25 to drive the PMOS pass transistor PPASS to provide the voltage level of the battery power source to the output terminal 55.
When bypass mode is enabled at the time t3, the analog multiplexer 20 immediately selects bypass gate control signal 50 to drive the gate of PMOS pass transistor PPASS, which is still at the voltage level of the power supply voltage source VDD. There is a delay time in biasing the nodes of the bypass control circuit 25 and pull the signal bypass gate control signal 50 to the voltage level of the ground reference voltage, during this time, if the output terminal 55 of the low dropout voltage regulator has a load 65 connected and all the charge will be provided by the external capacitors (not shown) and the output voltage will decrease as shown between the times t3 and t5.
At the time t6, the bypass signal 35 is deactivated, which causes the LDO enable signal to be activated by the bypass control circuit 20. The bypass gate control signal 50 is deactivated and the LDO gate control signal 15 is activated and thus the gate signal 25 begins to adjust the gate voltage level to adjust the voltage across the PMOS pass transistor PPASS to regulate the output voltage level 55.
In bypass mode, the LDO gate control signal 15 is pulled high as the LDO control circuit 10 is disabled, as described above. It takes time for all the internal nodes of LDO control circuit 10 to reach their required potential for the required load current. The charge during this time is provided by output decoupling capacitor. Loss of charge form the capacitor results in decrease in output voltage. The decrease in output voltage is function of the load current and output capacitor. For large load currents and small output capacitor “brown-out condition” may arise, thus resetting the device and causing the load current 60 to go to a zero level. The device will try to recycle and if the output voltage level 55 has not stabilized it, as at the time t7, the device will continue to recycle.